Error amplifier structures

ABSTRACT

Error amplifier structures are provided to generate an error signal in response to the difference between an input signal (e.g., a feedback current) and a reference signal (e.g., a bias current). Amplifier embodiments generally include a reference generator and a differencing amplifier. In at least one embodiment, the error generator is arranged to generate first and second bias voltages that correspond to the bias current. In at least one embodiment, the differencing amplifier is configured to provide a reference current to an output node in response to the first bias voltage, provide a feedback current to the output node in response to the second bias voltage, and generate an error current in response to a voltage at the output node. The error amplifier structures are suited for use in various systems such as negative switching regulators.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to error amplifiers and moreparticularly to error amplifiers for use in voltage boosting circuitssuch as negative switching regulators and charge pumps.

2. Description of the Related Art

Error amplifiers are configured to provide an error signal in responseto the difference between an operational signal (e.g., a feedbacksignal) and a reference signal. They are especially suited for use infeedback systems that control an output signal to have a desiredcorrespondence to a reference.

Exemplary feedback systems are negative switching regulators that arepowered by a supply voltage and provide a controlled output voltage witha polarity opposite that of the supply voltage. Error amplifiers forsuch systems have generally included an input stage, a gain stage, andan output stage. The input stage is typically configured tosymmetrically compare signals at a pair of input nodes to therebygenerate a difference signal. The gain stage provides a single-endederror signal with gained response to the difference signal and theoutput stage provides buffering while delivering the error signal to asystem port.

Although such error amplifiers can be configured to provide excellentperformance, they typically have a number of disadvantages that limittheir use in integrated circuits, e.g., they are complex, expensive, andrequire large compensation capacitors.

BRIEF SUMMARY OF THE INVENTION

The present disclosure is generally directed to error amplifierembodiments. The drawings and the following description provide anenabling disclosure and the appended claims particularly point out anddistinctly claim disclosed subject matter and equivalents thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic that illustrates an error amplifier embodiment ofthe present disclosure;

FIG. 2 is a schematic that illustrates another error amplifierembodiment;

FIG. 3 is a schematic that illustrates an error amplifier embodimentthat includes more than one differencing amplifier output;

FIG. 4 is a schematic that illustrates a comparator application of theerror amplifier of FIG. 2;

FIG. 5 is a schematic of a switching regulator system that includes theerror amplifier of FIG. 1; and

FIG. 6 is a schematic of a switching regulator system that includes theerror amplifier of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates an error amplifier 20 that is formed with a referencegenerator 24 and a differencing amplifier 44 that are arranged toprovide an error current 21 in response to a feedback current 23. Theerror amplifier 20 is especially suited for use with voltage boostingcircuits such as negative switching regulators and charge pumps.

The reference generator 24 is arranged to provide first and second biasvoltages to the differencing amplifier (at bias pins 37 and 38). Thedifferencing amplifier 44 is arranged to provide the reference current22 to an output node 49 in response to the first bias voltage, provide afeedback current 23 to the output node 49 in response to the second biasvoltage, and generate the error current 21 in response to a voltage atthe output node.

It is important to note that although the error amplifier of FIG. 1 isrealized with metal-oxide-semiconductor (MOS) transistors, it can, ingeneral, be realized with any transistors in which currents at currentterminals (e.g., sources and drains) respond to signals at controlterminals (e.g., gates).

In detail, FIG. 1 shows that the reference generator 24 includes areference resistor 26 with resistance R_(ref), a differential amplifier27 and a current transistor 28. The differential amplifier has aninverting input port coupled to the top of the reference resistor and anon-inverting input port coupled to receive a reference voltage V_(ref)at a reference port 29. The current transistor has a drain coupled tothe top of the reference resistor and a gate coupled to the output portof the differential amplifier. The reference generator 24 also has firstand second reference transistors 31 and 32 whose drains are coupledtogether. The second reference transistor is diode-coupled and the firstreference transistor is gate-coupled to the current transistor 28.

In operation, the current transistor 28 is biased on by the differentialamplifier and the high gain of the differential amplifier causes thevoltage at the top of the reference resistor to substantially equal thereference voltage V_(ref). A bias current I_(bias) equal toV_(ref)/R_(ref) is thereby driven through the reference resistor 26 bythe current transistor 28. Because the first reference transistor 31 isgate-coupled and source-coupled to the current transistor, it carries abias current 34 with amplitude substantially equal to I_(bias) anddirects this current through the diode-coupled second referencetransistor 32. Accordingly, the control terminals of the first andsecond reference transistors 31 and 32 provide first and second biassignals at bias ports 37 and 38 of the reference generator 24 whereinthese bias signals correspond to the reference current I_(ref).

The differencing amplifier 44 includes first and second amplifiertransistors 47 and 48 whose gates are respectively coupled to the biasports 37 and 38. The first amplifier transistor 47 is alsosource-coupled to the first reference transistor 31. In addition, thedrains of the first and second amplifier transistors are coupledtogether to form an output node 49 and the source of the secondamplifier transistor 48 is coupled to a feedback port 50. Thedifferencing amplifier also includes a third amplifier transistor 52that is arranged to provide the error current 21 at an output port 54 inresponse to an error signal at the output node 49.

In an exemplary operation of the differencing amplifier 44, the sourceof the second amplifier transistor 48 is coupled through a feedbackresistor 55 to an output voltage V_(out) which might, for example, bethe negative output voltage of a negative switching regulator. In thisexample, the error current 21 would represent a feedback signal that canbe processed (e.g., through a pulse-width modulator) into a gate signalfor a transistor switch of the negative switching regulator.

If the feedback current 23 exceeds the reference current 22 (i.e., theamplitude of the output voltage V_(out) is greater than desired), theoutput node 49 drops so that the third amplifier transistor 52 iscommanded to decrease the error current 21. If the feedback current 23drops below the reference current 22 (i.e., the amplitude of the outputvoltage V_(out) is less than desired), the output node 49 rises so thatthe third amplifier transistor 52 is commanded to increase the errorcurrent 21.

If the first and second amplifier transistors 47 and 48 are configuredto have the same size (e.g., equal gate widths) as the transistors inthe reference generator 24, the amplitude of the reference current 22will substantially equal the amplitude of bias current 34 through thefirst and second reference transistors 31 and 32. If the voltage drop inthe feedback resistor 55 equals the output voltage V_(out), then thegate-to-source voltage of the second amplifier transistor 48 will matchthat of the second reference transistor 32 so that the feedback current23 also substantially equals the amplitude of bias current 34. In thiscase, the voltage at the output node 49 will substantially be one-halfof the voltage supply V_(sply).

Preferably, however, the transistors in the reference generator 24(current transistor 28 and first and second reference transistors 31 and32) are configured with a size substantially less than that of thetransistors of the differencing amplifier. This does not alter theoperation described above but significantly reduces the current drawnfrom the voltage source V to thereby substantially enhance theamplifier's efficiency.

From the detailed description above, it is apparent that the referencegenerator 24 is arranged to generate the bias current 34 through itsfirst and second reference transistors 31 and 32 to thereby providefirst and second bias signals at the bias ports 37 and 38 thatcorrespond to the bias current. The error amplifier 44 is thenconfigured to:

-   -   a) provide the reference current 22 to the output node 49 in        response to the bias signal at bias port 37;    -   b) provide a feedback current 23 to the feedback port 50 in        response to the bias signal at bias port 38; and    -   c) generate the error current 21 in response to a voltage at the        output node 49.

These basic amplifier structures can be augmented to form other erroramplifier embodiments as indicated in FIG. 2 which illustrates an erroramplifier embodiment 60 which includes elements of the amplifier 20 withlike elements indicated by like reference numbers. In the erroramplifier embodiment 60, the reference generator 24 has been altered toa reference generator 62 that includes transistors 65 and 66. Thesetransistors are respectively coupled in cascode arrangements with thecurrent transistor 28 and the first reference transistor 31. Inaddition, the differencing amplifier 44 has been modified to adifferencing amplifier 65 that couples a transistor 67 in a cascodearrangement with the first amplifier transistor 47. Transistor 65 isarranged as a diode-coupled transistor to properly bias currents intransistors 66 and 67. In these cascode arrangements, the currenttransistor 28, first reference transistor 31 and first amplifiertransistor 47 act as common-gate stages to significantly increase outputimpedances at their drains and, thereby, increase amplifier gain.

The differencing amplifier 64 also includes a buffer transistor 68 thatis inserted as a source follower to drive the base of the thirdamplifier transistor 52. Current through the buffer transistor isprovided via an offset transistor 69 that is biased by the second biassignal at the bias port 38 of the reference generator 62. The buffertransistor 68 can be used to substantially reduce capacitive loading onthe output node 37.

When the error amplifier 60 is used, for example, in the feedback pathof a negative switching regulator, this loading reduction can move afeedback pole (associated with the first and second amplifiertransistors 47 and 48) to higher frequencies which significantlyenhances feedback bandwidth. In addition, the buffer transistor 68lowers the voltage at the gate of the third amplifier transistor 52 sothat this transistor can be safely realized as a low threshold voltage(low V_(t)) transistor whose faster response time can be advantageouslyused in feedback uses of the error amplifier 60.

The differencing amplifier 64 also inserts an output cascode transistor71 into a cascode arrangement with the third amplifier transistor 52.This insertion facilitates higher output voltage swings andsignificantly increases the output impedance at the output port 54 whichreduces the feedback degradation of Miller capacitance when the erroramplifier 60 is arranged in a feedback path (e.g., the feedback path ofa negative switching regulator).

When the error amplifier 60 is used in a feedback path, a compensationcapacitor 74 can be inserted in shunt before the feedback resistor 55 toinsert a dominant feedback pole that selectively determines the feedbackbandwidth. A second compensation capacitor 75 can be arranged inparallel with the feedback resistor 55 to insert a feedback zero thatcan be positioned to substantially cancel an undesired feedback pole andthereby enhance feedback stability.

Although FIG. 2 illustrates the addition of several structures to theerror amplifier 20 of FIG. 1, it should be understood that each can beused separately from the others or they can be used in variouscombinations to form different error amplifier embodiments.

The novel structure of the error amplifier 20 of FIG. 1 also facilitatesthe use of a single reference generator 24 for driving N differencingamplifiers 44. For example, FIG. 3 illustrates an error amplifier system80 in which N is 2 so that differencing amplifiers 44A and 44B are bothcoupled to the bias ports 37 and 38 of a single reference generator 24.Each of the error amplifiers 44A and 44B can form a portion of arespective feedback loop in which a feedback current (e.g., from anegative switching regulator) is conducted through the feedback port 50and, in response, an error current 21 is generated. It is apparent thatthe parts count can be significantly reduced as the number N ofdifferencing amplifiers increases.

FIG. 4 illustrates a comparator 90 that includes elements of the erroramplifier 60 of FIG. 2 with like elements indicated by like referencenumbers. The comparator 60, however, eliminates the buffer transistor68, offset transistor 69, and output cascode transistor 71 and, instead,inserts a fourth amplifier transistor 53. This fourth amplifiertransistor is drain-coupled to the third amplifier transistor 52 and hasits gate driven by the drain of the first amplifier transistor 47. Thethird and fourth amplifier transistors 52 and 53 are thus arranged toform a complementary common-source output stage 94 that drives theoutput port 54. More particularly, they form an inverter whose output atthe output port 54 moves oppositely to input voltages across the firstamplifier transistor 47.

Because the first and second reference transistors 31 and 32 and thefirst, second and third amplifier transistors 47, 48 and 52 can be sizedto operate with substantially the same current density (to thereby havesubstantially the same gate-to-source voltage V_(gs)), the output node49 is at the same voltage level as the coupled drains of the first andsecond reference transistors. Accordingly, the potential at the outputnode 49 is on the verge of turning on the third amplifier transistor 52when the voltage at the inverting input 50 is at the comparator's groundlevel (level of the sources of the second reference transistor 32 andthe third amplifier transistor 52).

As the inverting input voltage drops and rises from the comparator'sground level, the output of the inverter (that is formed by the thirdand fourth amplifier transistors 52 and 53, moves oppositely. That is,the output voltage V_(out) at the output port 54 rapidly transitions inthe opposite direction to thereby provide knowledge of the voltage atthe inverting input port 50. Essentially, the voltage at the invertinginput 50 is compared to the comparator's ground level.

The comparator 90 is especially useful in hysteric mode control(sometimes called bang-bang control) in which the output voltage of aswitching regulator is controlled by a control loop. In hysteric loopcontrol, however, the control loop includes a comparator rather than anerror amplifier. If the regulator's output voltage is too small, theregulator's power transistor is turned on by the comparator—if it is toolarge, the transistor is turned off by the comparator. Accordingly, theoutput window of the regulator can be controlled to be within a hystericwindow.

Error amplifier embodiments of the disclosure can be used to facilitatecontrol of a variety of negative switching regulators. For example, FIG.5 illustrates a switching regulator system 100 that includes the erroramplifier 20 of FIG. 1, a negative switching regulator 102, and apulse-width-modulation (PWM) generator 103.

The regulator includes a transistor switch 104 and a diode 105 arrangedin series between regulator input and output ports 107 and 108. Acapacitor 109 shunts the output port and an inductor 110 is arranged inshunt between the transistor and the capacitor. An output load 111 canbe driven at the output port with the feedback resistor 55 (introducedin FIG. 1) coupled between the feedback port 50 of the regulator 20 andthe top of the output port 108 of the regulator.

In operational cycles of the system 100, the transistor 104 turns on ina first portion of each cycle to thereby increase current along aninductor charging path 112 which passes through the inductor 110. In asecond portion of each operational cycle, the transistor 104 is turnedoff so that the inductor is free to discharge energy along an inductordischarging path 114 to thereby transfer energy to the capacitor 109 andthe load 111.

Current ramps up in the inductor during the first portion of eachoperational cycle and ramps down during the second portion. Energystored in the inductor during the first portion is transferred to thecapacitance and the load in the second portion. The capacitor 109supports the load and sustains the output voltage V_(out) across theoutput port 108 during the first portion while the inductor is charging.The transistor 104 switches a positive voltage to the inductor to storeenergy but, because the inductor discharges along the discharge path110, a negative voltage is sustained across the load 111.

The magnitude of the output voltage at the output port 108 determinesthe magnitude of the feedback current 23 in the second-amplifiertransistor 48 of the error amplifier 20. This, in turn, determines themagnitude of the feedback current 21 that flows out of the PWM generator102. This generator is configured to vary the pulse width applied to theswitch transistor 104 in response to the magnitude of the feedbackcurrent. The signal out of the PWM generator varies the duty cycle(ratio of off time to on time) of the switch transistor 104. That is,the PWM generator has a transfer function of an output duty cycle inresponse to an input current.

Thus, the PWM generator biases on the switch transistor 104 during thefirst portion of each operational cycle and bias it off during thesecond portion wherein the duration of the first portion is a functionof the feedback current 21. If the magnitude of the output voltageV_(out) across the load 111 is too large, for example, the feedbackcurrent 23 increases to thereby increase the error current 21 and reducethe duty cycle of the switch transistor 104.

In a system embodiment, the PWM generator may receive an additionalfeedback signal from a current sensor 115 that senses variations in thecurrent of the inductor charging path 112. This allows the system 100 torespond more quickly to input current variations than it wouldotherwise.

FIG. 6 illustrates another regulator system 120 that combines the erroramplifier 60 of FIG. 2 with a negative switching regulator 121 that isconfigured as a charge pump. The charge pump includes diodes 122 and 123arranged in series between the output port 54 of the amplifier and aload 124 which is arranged across an output port 125 of the regulator. Acapacitor 127 is coupled across the load, a voltage oscillator 128 iscoupled to ground and another capacitor 126 is coupled between theoscillator and a junction between the diodes 122 and 123. The top of theload 124 is coupled to the feedback port 50 of the error amplifier 60via the resistor 55 and shunt capacitor 75 that were introduced in FIG.5.

The voltage oscillator 128 is configured to provide a first voltage inthe first portion of each operational cycle and a second voltage in thesecond portion. For illustrative purposes, assume the first and secondvoltages are +10V and 0V. Also assume that the output port 54 of theamplifier 60 is controlled to be +3V and that the first and secondportions are equal. In the first portion, the diode 122 is forwardbiased and −7V is established across the first capacitor 126. In thesecond portion, the voltage across the first capacitor 126 istransferred to be across the second capacitor 127. Accordingly, −7V isestablished across the load 124.

In operation of the system 120, a voltage at the output node 49 isestablished by the difference between the reference current 22 and thefeedback current 23 that flows to the top of the second capacitor 127.The error current 21 is pulled from the first capacitor 126 in responseto the voltage at the output node 49 of the amplifier 60. The errorcurrent 21 and the feedback current 23 establish voltages across thefirst and second capacitors 126 and 127 in the first and second portionsof each operational cycle and this process establishes and controls thesteady-state negative output voltage V_(out) across the output load 124.Although the diodes 122 and 123 do not respond to signals at controlterminals (as in transistors), they essentially act as switching devicesin the regulator 121.

Although the regulator system 100 has been configured with a buck-boostregulator 102, error amplifier embodiments (e.g., as shown in FIGS. 1-4)may be used with various negative switching regulator structures (e.g.,offset buck and ‘Cuk regulators) and also with negative charge pumps(such as the embodiment of FIG. 6). When the error amplifier embodimentsare powered, instead, by a positive supply, they may be used withvarious positive switching regulators (e.g., buck, boost, non-invertingbuck-boost, Sepik, inverse Sepik, and buck²) and also with positivecharge pumps.

As previously noted, the amplifier embodiments of FIGS. 1-6 areillustrated with the use of MOS transistors but they can also berealized with other transistor families. The embodiments provide highgain (e.g., >50 dB), have a low parts count, can be fabricated with lowvoltage MOS technologies (e.g., 0.35 μm) are especially suited forrealization as an integrated circuit with a limited number of elements(e.g., the compensation capacitors 74 and 75 of FIG. 1) positionedexternally to the integrated circuit.

The amplifier and comparator embodiments provide excellent loadtransient response and, in contrast to many error amplifierconfigurations, the circuit arrangement is simple and only a singlefeedback resistor is needed (which further reduces the parts count). Asshown in FIG. 3, a number of switching regulators can be controlled withrespective differencing amplifiers that each interfaces with a singlereference generator. Because only a single V_(ref) pin (29 in FIG. 1) isrequired, this feature frees up a number of integrated circuit pins forother uses.

Another advantage of this disclosure's amplifier embodiments is relatedto Miller effect which refers to an increase in the equivalent inputcapacitance of an inverting voltage amplifier due to amplification ofamplifier capacitance. The presence of the Miller effect complicates thestability compensation required by a control loop. Because the presentamplifier embodiments do not generate signal inversion, this problem isavoided and loop compensation is significantly simplified.

The embodiments of the invention described herein are exemplary andnumerous modifications, variations and rearrangements can be readilyenvisioned to achieve substantially equivalent results, all of which areintended to be embraced within the spirit and scope of the appendedclaims

1. An amplifier to provide an error current in response to a feedbackcurrent, the amplifier comprising: a reference generator arranged togenerate a bias current in first and second reference transistors; afirst amplifier transistor coupled to generate a reference current inresponse to a control terminal of said first reference transistor; asecond amplifier transistor coupled through second control terminals tosaid second reference transistor, coupled through current terminals tosaid first amplifier transistor to define an output node, and having asecond current terminal to receive said feedback current; and a thirdamplifier transistor to provide said error current in response to anerror signal at said output node.
 2. The amplifier of claim 1, whereinsaid second reference transistor is a diode-coupled transistor that iscoupled to said first reference transistor through current terminals. 3.The amplifier of claim 1, wherein said reference generator includes: areference resistor; a differential amplifier having a first input portcoupled to said reference resistor and a second input port to receive areference voltage; and a current transistor coupled through controlterminals with said first reference transistor and coupled to drive acurrent through said reference resistor in response to a signal at anoutput port of said amplifier.
 4. The amplifier of claim 3, furtherincluding first, second and third cascode transistors coupled togetherthrough control terminals and inserted in a cascode relationship withsaid current transistor, said first reference transistor, and said firstamplifier transistor respectively wherein said first cascode transistoris diode-coupled.
 5. The amplifier of claim 1, wherein said first andsecond reference transistors and said first, second and third amplifiertransistors are metal-oxide-semiconductor transistors.
 6. The amplifierof claim 1, further including: a buffer transistor inserted to drivesaid third amplifier transistor in response to said error signal at saidoutput node; and an offset transistor coupled through current terminalsto said buffer transistor and coupled through control terminals to saidsecond amplifier transistor.
 7. The amplifier of claim 1, furtherincluding an output cascode transistor inserted in a cascoderelationship with said third amplifier transistor.
 8. An amplifier toprovide an error current in response to a feedback current, theamplifier comprising: a reference generator having first and secondreference transistors and arranged to generate a bias current throughsaid first and second reference transistors; and a differencingamplifier configured to: provide a reference current to an output nodein response to a signal at a first control terminal of said firstreference transistor; provide a feedback current to said output node inresponse to a signal at a second control terminal of said secondreference transistor; and generate said error current in response to avoltage at said output node.
 9. The amplifier of claim 8, wherein saiddifferencing amplifier includes: a first amplifier transistor having acontrol terminal coupled to said first control terminal and a currentterminal coupled to said output node; a second amplifier transistorhaving a control terminal coupled to said second control terminal, afirst current terminal coupled to said output node, and a second currentterminal positioned to receive said feedback current; and a thirdamplifier transistor to provide said error current.
 10. The amplifier ofclaim 9, further including: a buffer transistor inserted to drive saidthird amplifier transistor in response to said error signal at saidoutput node; and an offset transistor coupled through current terminalsto said buffer transistor and coupled through control terminals to saidsecond amplifier transistor.
 11. The amplifier of claim 9, furtherincluding an output cascode transistor inserted in a cascoderelationship with said third amplifier transistor.
 12. The amplifier ofclaim 8, wherein said second reference transistor is a diode-coupledtransistor that is coupled to said first reference transistor throughcurrent terminals and wherein said reference generator further includes:a reference resistor; a differential amplifier having a first input portcoupled to said reference resistor and a second input port to receive areference voltage; and a current transistor coupled through controlterminals with said first reference transistor and coupled to drive acurrent through said reference resistor in response to a signal at anoutput port of said amplifier.
 13. The amplifier of claim 12, furtherincluding first, second and third cascode transistors coupled togetherthrough control terminals and inserted in a cascode relationship withsaid current transistor, said first reference transistor, and said firstamplifier transistor respectively wherein said first cascode transistoris diode-coupled.
 14. The amplifier of claim 13, further including afourth amplifier transistor coupled to be driven by said third cascodetransistor and said first amplifier transistor and drain-coupled to saidthird amplifier transistor.
 15. A switching regulator system,comprising: a negative switching regulator configured to generate anoutput voltage in response to a pulse-width modulation signal; apulse-width modulator to provide said pulse-width modulation signal inresponse to an error current; a feedback resistor coupled to receivesaid output voltage to provide a feedback current; and an amplifier toprovide said output current signal in response to said feedback
 16. Theamplifier of claim 12, further including first, second and third cascodetransistors a reference generator arranged to generate a bias current infirst and second reference transistors; a first amplifier transistorcoupled to generate a reference current in response to a controlterminal of said first reference transistor; a second amplifiertransistor coupled through second control terminals to said secondreference transistor, coupled through current terminals to said firstamplifier transistor to define an output node, and having a secondcurrent terminal to carry said feedback current; and a third amplifiertransistor to provide said error current in response to an error signalat said output node.
 17. The system of claim 15, wherein said negativeswitching regulator is a negative current pump.
 18. The system of claim15, wherein said reference generator includes: a reference resistor; adifferential amplifier having a first input port coupled to saidreference resistor and a second input port to receive a referencevoltage; and a current transistor coupled through control terminals withsaid first reference transistor and coupled to drive a current throughsaid reference resistor in response to a signal at an output port ofsaid amplifier.
 19. The system of claim 15, further including first,second and third cascode transistors coupled together through controlterminals and inserted in a cascode relationship with said currenttransistor, said first reference transistor, and said first amplifiertransistor respectively wherein said first cascode transistor isdiode-coupled.
 20. The system of claim 15, further including: a buffertransistor inserted to drive said third amplifier transistor in responseto said error signal at said output node; and an offset transistorcoupled through current terminals to said buffer transistor and coupledthrough control terminals to said second amplifier transistor.